Histogramer

Histogramer is used to manage a histogram.

Key features

Histogram boxes are stored inside Block RAM
Each box will be sequentially cleared after the reset
A new input request will increment the histogram box based on an input value
Read request will read the content of a given box
Read requests can be set to clear box content after execution
Input or read request priority can be set
A new read or write request can be processed in every clock cycle
Collisions during read-modify-write access to Block RAM are handled

Component port and generics description

ENTITY HISTOGRAMER IS

Generics

Generic	Type	Default	Description
INPUT_WIDTH	integer	UNDEFINED	Width of input values
BOX_WIDTH	integer	UNDEFINED	Width of one histogram box (number of values in a given range) Box probably overflowed when its value equals 2**BOX_WIDTH-1
BOX_CNT	integer	UNDEFINED	Number of histogram boxes (defines histogram precision)
READ_PRIOR	boolean	false	Defines if read or write should occur when both happen at the same time
CLEAR_BY_READ	boolean	true	Defines if read should erase box content
CLEAR_BY_RST	boolean	true	Defines if BRAM should be sequentially erased after reset

Ports

Port	Type	Mode	Description
CLK	std_logic	in
RST	std_logic	in
RST_DONE	std_logic	out
=====	Input interface	=====	=====
INPUT_VLD	std_logic	in
INPUT	std_logic_vector(INPUT_WIDTH - 1 downto 0)	in
=====	Read interface	=====	=====
READ_REQ	std_logic	in	Request to read box specified by READ_ADDR
READ_ADDR	std_logic_vector(log2(BOX_CNT) - 1 downto 0)	in	Box adress
READ_BOX_VLD	std_logic	out	The requested box is valid
READ_BOX	std_logic_vector(BOX_WIDTH - 1 downto 0)	out	Requested box

Instance template

histogrammer_i : entity work.HISTOGRAMER
generic map(
    INPUT_WIDTH             => INPUT_WIDTH,
    BOX_WIDTH               => BOX_WIDTH,
    BOX_CNT                 => BOX_CNT,
    READ_PRIOR              => READ_PRIOR,
    CLEAR_BY_READ           => CLEAR_BY_READ,
    CLEAR_BY_RST            => CLEAR_BY_RST
)
port map(
    CLK                     => CLK,
    RST                     => RST,
    RST_DONE                => rst_done,

    INPUT                   => input,
    INPUT_VLD               => input_vld,

    READ_REQ                => read_req,
    READ_ADDR               => read_addr,
    READ_BOX_VLD            => read_box_vld,
    READ_BOX                => read_box
);