MFB Splitter Simple

ENTITY MFB_SPLITTER_SIMPLE IS

This component transmits received packets on one interface to one out of the two outputs according to the select bit.

Generics

Generic

Type

Default

Description

REGIONS

natural

2

number of regions in a data word

REGION_SIZE

natural

8

number of blocks in a region

BLOCK_SIZE

natural

8

number of items in a block

ITEM_WIDTH

natural

8

number of bits in an item

META_WIDTH

natural

8

number of bits for metadata in a single region

Ports

Port

Type

Mode

Description

CLK

std_logic

in

RST

std_logic

in

=====

rx interface

=====

=====

RX_MFB_SEL

std_logic_vector(REGIONS-1 downto 0)

in

is only valid with asserted sof signal

RX_MFB_DATA

std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)

in

RX_MFB_META

std_logic_vector(REGIONS*META_WIDTH-1 downto 0)

in

RX_MFB_SOF

std_logic_vector(REGIONS-1 downto 0)

in

RX_MFB_EOF

std_logic_vector(REGIONS-1 downto 0)

in

RX_MFB_SOF_POS

std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)

in

RX_MFB_EOF_POS

std_logic_vector(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0)

in

RX_MFB_SRC_RDY

std_logic

in

RX_MFB_DST_RDY

std_logic

out

=====

tx interface 0

=====

=====

TX0_MFB_DATA

std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)

out

TX0_MFB_META

std_logic_vector(REGIONS*META_WIDTH-1 downto 0)

out

TX0_MFB_SOF

std_logic_vector(REGIONS-1 downto 0)

out

TX0_MFB_EOF

std_logic_vector(REGIONS-1 downto 0)

out

TX0_MFB_SOF_POS

std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)

out

TX0_MFB_EOF_POS

std_logic_vector(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0)

out

TX0_MFB_SRC_RDY

std_logic

out

TX0_MFB_DST_RDY

std_logic

in

=====

tx interface 1

=====

=====

TX1_MFB_DATA

std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)

out

TX1_MFB_META

std_logic_vector(REGIONS*META_WIDTH-1 downto 0)

out

TX1_MFB_SOF

std_logic_vector(REGIONS-1 downto 0)

out

TX1_MFB_EOF

std_logic_vector(REGIONS-1 downto 0)

out

TX1_MFB_SOF_POS

std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)

out

TX1_MFB_EOF_POS

std_logic_vector(REGIONS*log2(REGION_SIZE*BLOCK_SIZE)-1 downto 0)

out

TX1_MFB_SRC_RDY

std_logic

out

TX1_MFB_DST_RDY

std_logic

in

MFB Splitter Simple Gen

ENTITY MFB_SPLITTER_SIMPLE_GEN IS

This is a 1:N MFB splitter. RX_MFB_SEL selects the output for each frame. The whole RX word is sent to every output in the same clock cycle. Each output gets the word with the SOFs and EOFs of the other outputs masked out. TX_MFB_SRC_RDY of an output stays low when the word carries no frame for that output. The latency is one clock cycle.

Warning

An RX word is taken only once every output can accept it, so the slowest output stops all the others.

Generics

Generic

Type

Default

Description

SPLITTER_OUTPUTS

integer

8

Number of splitter outputs.

REGIONS

integer

4

Number of Regions in a word.

REGION_SIZE

integer

8

Number of Blocks in a Region.

BLOCK_SIZE

integer

8

Number of Items in a Block.

ITEM_WIDTH

integer

8

Width of one Item (in bits).

META_WIDTH

integer

1

Width of MFB metadata (in bits).

DEVICE

string

“AGILEX”

FPGA device name: ULTRASCALE, STRATIX10, AGILEX, …

Ports

Port

Type

Mode

Description

=====

Clock and Reset

=====

=====

CLK

std_logic

in

RESET

std_logic

in

=====

RX interface

=====

=====

RX_MFB_SEL

std_logic_vector(REGIONS*max(1,log2(SPLITTER_OUTPUTS))-1 downto 0)

in

One select bit for each stage (and for each region ofc), bit RX_MFB_SEL(0)(x) is for Stage 0, and so on. Expected to be valid with SOF!

RX_MFB_DATA

std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)

in

RX_MFB_META

std_logic_vector(REGIONS*META_WIDTH-1 downto 0)

in

Valid whenever, metadata is split by words

RX_MFB_SOF

std_logic_vector(REGIONS-1 downto 0)

in

RX_MFB_EOF

std_logic_vector(REGIONS-1 downto 0)

in

RX_MFB_SOF_POS

std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)

in

RX_MFB_EOF_POS

std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)

in

RX_MFB_SRC_RDY

std_logic

in

RX_MFB_DST_RDY

std_logic

out

=====

TX interface

=====

=====

TX_MFB_DATA

slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0)

out

TX_MFB_META

slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(REGIONS*META_WIDTH-1 downto 0)

out

Valid whenever, metadata is split by words

TX_MFB_SOF

slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(REGIONS-1 downto 0)

out

TX_MFB_EOF

slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(REGIONS-1 downto 0)

out

TX_MFB_SOF_POS

slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0)

out

TX_MFB_EOF_POS

slv_array_t (SPLITTER_OUTPUTS-1 downto 0)(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0)

out

TX_MFB_SRC_RDY

std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)

out

TX_MFB_DST_RDY

std_logic_vector(SPLITTER_OUTPUTS-1 downto 0)

in