.. readme.rst: Documentation of single component
.. Copyright (C) 2021 CESNET z. s. p. o.
.. Author(s): Tomáš Beneš <xbenes55@stud.fit.vutbr.cz>
..
.. SPDX-License-Identifier: BSD-3-Clause

.. _fifox:

FIFOX
-------

.. vhdl:autoentity:: FIFOX
   :noautogenerics:

Block diagram
^^^^^^^^^^^^^

TODO- Přidat blokový diagram komponenty FIFOX

Verification
^^^^^^^^^^^^

Verification is coverage oriented. There is code coverage turned on. The code coverage report can be generated by uncommenting one line in top_level.fdo. Both input and output interfaces of component are connected by MVB interfaces to the verification environment. The scoreboard checks that the data that are written into component are readed in  correct order at output interface.

Verification block diagram
^^^^^^^^^^^^^^^^^^^^^^^^^^

.. image:: doc/fifox_ver.svg
    :width: 100 %


There are 3 tests. The first 2 are most random and are designed to verify correct functionality in classic use. The 3th one is designed to check functionality when data are more often written and less often readed.